[Noticias-IIE] IIE: IEEE CASS Uruguay - Conferencia Dr. Ram Achar

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IEEE CASS Uruguay - Conferencia Dr. Ram Achar 
de María Misa -  Wednesday, 2 de May de 2012, 14:26
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El capítulo Uruguay de la IEEE Circuits and Systems Society, invita a
la conferencia:

MEETING THE SIGNAL INTEGRITY CHALLENGES OF HIGH-SPEED CIRCUIT AND SYSTEMS
Dr. Ram Achar – IEEE Distinguished Lecturer
http://web.doe.carleton.ca/~achar/ [http://web.doe.carleton.ca/~achar/]

Viernes 4 de mayo de 2012 – 18:00hs.
Facultad de Ingeniería UdelaR , Julio Herrera y Reissig 565 Salón 002.

Participación libre.

Abstract:
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The intense drive for signal integrity has been at the forefront of
rapid and new development in CAD algorithms focused on high-speed
circuits and systems. With increasing demands for high signal speeds
coupled with decreasing feature sizes, interconnect effects such as
signal delay, distortion and crosstalk become the dominant factors
limiting the performance of high-speed systems. On the other hand,
interconnect structures can be diverse and present at any of the
hierarchical packaging levels including integrated circuits, printed
circuit boards, multi-chip modules and backplanes. If not considered
during the design stage, interconnect effects can cause failed
designs. Since extra iterations in the design cycle are costly,
accurate prediction of these effects is a necessity in high-speed
designs. Although conventional CAD tools such as SPICE are used
routinely by many engineers for simulation and general circuit
analysis, these tools do not handle adequately the new emerging
challenges of interconnect effects.

In this talk, high-frequency issues and signal integrity in high-speed
designs will be discussed. Advanced signal integrity
modeling/simulation strategies applicable to various levels of system
hierarchy will be described. Also the underlying concepts leading to
high-frequency effects, signal parameters and time-frequency relations
will be reviewed. Particular emphasis will be placed on distributed,
long and large coupled interconnects. Modeling approaches to handle
high-frequency current distribution related effects, such as skin,
proximity and edge effects will be considered. Particular emphasis
will be placed on preserving the macromodel properties, such
stability, causality and passivity. Various levels of interconnect
modeling will be considered and the applications cover wide spectrum
of on-chip, multichip, packages, printed circuit boards,
backplanes/connectors.


Brief bio of Prof. Achar:
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Prof. Achar is an active researcher contributing to the advancement of
computer-aided design tools and methodologies for analysis of
high-frequency circuits and systems. He has published over 170
peer-reviewed articles in international journals/conferences, six
multimedia books on signal integrity and five chapters in different
books.

Dr. Achar currently is a professor in the department of electronics
engineering at Carleton University. Prior to joining Carleton
university faculty (2000), he served in various capacities in leading
research labs, including T. J. Watson Research Center, IBM, New York
(1995), Larsen and Toubro Engineers Ltd., Mysore (1992), Central
Electronics Engineering Research Institute, Pilani, India (1992) and
Indian Institute of Science, Bangalore, India (1990). His research
interests include signal/power integrity analysis, circuit simulation,
parallel and numerical algorithms, EMC/EMI analysis, microwave/RF
algorithms, modeling/simulation methodologies for sustainable and
renewable energy, and mixed-domain analysis.

Dr. Achar received several prestigious awards, including Carleton
university research achievement awards (2010 & 2004), NSERC (Natural
Science and Engineering Research Council) doctoral medal (2000),
University Medal for the outstanding doctoral work (1998), Strategic
Microelectronics Corporation (SMC) Award (1997) and Canadian
Microelectronics Corporation (CMC) Award (1996). He was also a
co-recipient of the IEEE advanced packaging best transactions paper
award (2007). His students have won numerous best student paper awards
in international forums.

Dr. Achar currently is a Distinguished Lecturer (DLP) of the IEEE
Circuits and Systems Society (CASS). Previously, he served as the
general co-chair of IEEE international conference on Electrical
Performance of Electronic Packages & Systems (EPEPS-2010,2011) and as
International Guest Faculty on the invitation of the Dept. of
Information Technology of Govt. of India, under the SMDP-II program.
He also currently serves on the executive/steering/technical-program
committees of several leading IEEE international conferences, such as
EPEPS, EDAPS, ECTC, SPI, ASP-DAC etc. and in the technical committees,
EDMS (TC-12 of CPMT) and CAD (MTT-1). He is a founding faculty member
of the Canada-India Center of Excellence, a member of the Canadian
standards committee on nanotechnology, chair of the joint chapters of
CAS/EDS/SSC societies of the IEEE Ottawa Section, and is a consultant
for several leading industries focused on high-frequency circuits,
systems and tools. Dr. Achar is a practicing professional engineer of
Ontario.
He received the B. Eng. degree in electronics engineering from
Bangalore University, India in 1990, M. Eng. degree in
micro-electronics from Birla Institute of Technology and Science,
Pilani, India in 1992 and the Ph.D. degree from Carleton University in
1998.

For more details about Dr. Achar, his Research
Activities/Contributions and Publications, Please visit:
http://web.doe.carleton.ca/~achar/ [http://web.doe.carleton.ca/~achar/]


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